High-Yield of Memory Elements from Carbon Nanotube Field-Effect Transistors with Atomic Layer Deposited Gate Dielectric

Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. We find that this memory effect can be controlled by carefully designing the gate dielectric in nm-thin layers. We have made atomic layer depositions (ALD) of HfO2 and TiO2 in a triple-layer configuration, for which we achieve CNT FETs with consistent and narrowly distributed memory effects in their transfer characteristics. The study includes more than 90 CNT FETs, providing a solid basis for statistics on the hysteresis seen in five different CNT-gate configurations.